Integrated circuits such as integrated circuit memory devices generally continue to increase in integration density. With increasing integration density, each active device such as a transistor generally decreases in area. In order to maintain increasing integration densities, it is also generally desirable for the isolation regions that isolate active devices from one another, to also shrink in size. Moreover, as integration densities continue to increase, and the number of active devices in an integrated circuit continue to increase, the interconnection or wiring between active devices may also limit the integration density. Accordingly, it is also desirable to decrease the size of the interconnections in the integrated circuit.
One example of an integrated circuit is a Static Random Access Memory (SRAM) device. As is well known to those having skill in the art, an SRAM includes an array of memory cells that can store data without the need to refresh the cells. As the number of cells that are integrated in an integrated circuit continues to increase, the area in an integrated circuit that is taken up by a unit memory cell generally continues to decrease. As the integration density continues to increase, it is also generally desirable for the power consumption of each cell to also decrease. Finally, it is also desirable for the operation and speed of each unit cell to increase.
In order to provide high integration density, low power consumption and high speed operation, a complementary transistor SRAM cell has been proposed. A complementary transistor SRAM cell, also referred to as a CMOS SRAM cell, uses a pair of cross-coupled CMOS inverters to store data.
Unfortunately, since the CMOS SRAM cell uses complementary transistors in a single unit cell, separate n-wells and p-wells are generally used for each unit cell. Since separate wells are used, it is generally desirable to also provide an isolating region to isolate the n-well from the p-well. Unfortunately, the isolating region may increase the unit cell size. Moreover, in order to provide the cross-coupled inverters, a pair of storage nodes generally are provided internal to the cell. The internal cell wiring including the storage nodes may also increase the cell size.
Referring now to FIG. 1A, a conventional CMOS SRAM cell is shown. The SRAM cell includes a pair of CMOS inverters. The first CMOS inverter comprises an n-channel MOS transistor 20a and a p-channel MOS transistor 21a. The second CMOS inverter includes n-channel MOS transistor 20b, and p-channel MOS transistor 21b. The first and second CMOS inverters are cross-coupled by connecting the gates of the MOS transistors 20a and 21a to a storage node 25b that is also connected between the source/drain regions of MOS transistors 20b and 21b. Similarly, the gates of the MOS transistors 20b and 21b are connected to a storage node 25a between the source/drain regions of MOS transistors 20a and 21a.
Continuing with the description of FIG. 1A, the sources of the p-channel MOS transistors 21a and 21b are connected to a power supply voltage VCC and the sources of the n-channel MOS 20a and 20b are connected to ground voltage VSS. The storage nodes 25a and 25b are connected to n-channel transfer transistors 22a and 22b, respectively. The transfer transistors are also referred to as pass transistors. The gates of the transfer transistors 22a and 22b are connected to a word line WL and the respective drains thereof are connected to complementary bit lines BL and BLB. Thus, complementary data is stored at storage nodes 25a and 25b, without the need to refresh the cell.
Referring now to FIG. 1B, a cross-section of a storage node 25a or 25b of FIG. 1A is illustrated. As shown, a source/drain region 110 of an n-channel MOS transistor 20a (or 20b) is formed in a p-well region of an integrated circuit substrate such as a semiconductor substrate 100. A source/drain region 113 of a p-channel MOS transistor 21a (or 21b) is formed in an n-well region of semiconductor substrate 100. The source/drain regions 110 and 113 are isolated from each other by an isolation region 101. Isolation region 101 may be formed by LOCal Oxidation of Silicon (LOCOS) or other conventional techniques. A gate insulating layer 40, a gate electrode 50, a capping insulating layer 60 and a gate sidewall spacer 70-1 may also be provided.
Still referring to FIG. 1B, an interlayer dielectric layer 150 is provided. A metal layer 160 connects the drain 110 of MOS transistor of 20a (or 20b) to the drain 113 of MOS transistor 21a (or 21b) to form the storage node 25a (or 25b). Accordingly, as shown in FIG. 1B, a conventional CMOS SRAM cell may have a large unit cell size because n-wells and p-wells are formed in each unit cell. The isolation region 101 and the internal wiring layer 160 may consume excessive unit cell area and may limit denser integration of the SRAM unit cell.